1. Field of the Invention
The present invention relates to communication systems. In particular, the present invention relates to the encoding and decoding of the Turbo code for use in an integrated modem system.
2. Description of Related Art
Coded digital communication techniques play an important role in modern communication systems. The objectives of error-correcting coding and decoding of information include the improvement of communication reliability and efficiency. In 1948, Claude Shannon demonstrated that by proper encoding and decoding of information, errors induced by a noisy channel could be reduced to any desired level, subject to a code rate constraint.
A channel encoder is characterized by three parameters: (1) the number of codewords in the codeword dictionary, or simply the code, Mc; (2) the dimensionality (codeword length) of the code Nc; and (3) the code rate rc defined as rc=log2 Mc/Nc bits/dimension. There are two types of code: the linear block code and convolutional codes. The linear (Nc, Kc) block code can be used for error control purposes by partitioning the data stream into blocks containing Kc bits each. An Nc-symbol codeword is formed for transmission by using an encoding rule to associate the r=Ncxe2x88x92Kc parity check bits with each Kc data bits. In contrast, the encoded data in convolutional codes do not have a simple block structure. A convolutional encoder operates on the input bit stream such that each information bit can affect a finite number of consecutive symbols in the encoder output.
Techniques for encoding and decoding convolutional codes are well known. The Viterbi algorithm (VA) is an elegant and efficient method for performing maximum likelihood (ML) decoding of convolutional codes. Powerful error-correction capability can be obtained by concatenating a Viterbi decoded convolutional code with a Reed-Solomon (RS) block code. The theory, design, and performance of the convolutional codes are discussed extensively in literature. Examples of the literature include xe2x80x9cDigital Communication Techniques: Signal design and detectionxe2x80x9d by Marvin K. Simon, Sami M. Hinedi, and William C. Lindsey, published by Prentice Hall, 1995, xe2x80x9cAdvanced Digital Communications: Systems and signal processing techniquesxe2x80x9d, edited by Kamilo Feher, published by Prentice Hall, 1987.
Turbo code is a recently discovered class of forward error correcting (FEC) codes that has performance approaching the theoretical limit suggested by the Shannon coding theorem. Turbo code therefore is attractive for high performance communication systems. The theory and design techniques of turbo code can be found in literature. Examples of turbo code literature include the paper xe2x80x9cTurbo Codes for PCS Applicationsxe2x80x9d by D. Divsalar and F. Pollara of Jet Propulson Laboratory, California Institute of Technology, Pasadena, Calif., and U.S. Pat. No. 5,446,747 issued to Berrou.
However, the implementation of turbo code in an integrated modem environment presents a number of challenges. First, the code should operate with different waveforms having different types of modulation and different data rates. Second, the implementation should be compatible with the existing code word such as the Reed-Solomon code for various modes. Third, the implementation should be compatible with standard clock rate used in the system. Fourth, the amount of hardware including interleaving buffers should be reasonable.
Accordingly, there is a need in the technology to provide a flexible and efficient technique to implement an encoder and decoder using the turbo code in an integrated modem system.
The present invention is a method and apparatus for encoding and decoding a turbo code. In the encoder, an interleaver interleaves and delays a block of input bits to generate interleaved input bits and delayed input bits. A first encoder generates a first, second, and third encoded bits. A second encoder generates a fourth encoded bit. A symbol generator generates a plurality of symbols which correspond to the input bits. In a decoder, a sync search engine detects a synchronizing pattern and extracts symbols from the encoded bits. An input buffer is coupled to the sync search engine to store the extracted symbols. A first soft-in-soft-out (SISO1) is coupled to the input buffer to generate a first soft decision set based on the extracted symbols. An interleaver is coupled to the SISO1 to interleave the first soft decision set. A second soft-in-soft-out (SISO2) is coupled to the input buffer and the interleaver to generate a second soft decision set. A de-interleaver is coupled to the SISO2 to de-interleave the second soft decision set. An adder is coupled to the SISO1 and the de-interleaver to generate a hard decision set.